1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a semiconductor memory apparatus and a method of controlling the same.
2. Related Art
Volatile semiconductor memory apparatuses cannot maintain original data levels because data values stored in memory cells (hereinafter, simply referred to as “cells”) are changed as time passes. Therefore, a periodic refresh operation is essential to hold the data values that are stored in the cells.
Further, the semiconductor memory apparatus includes cell blocks, each of which includes a plurality of general cells, and redundant cells so as to repair defective cells among the general cells.
Therefore, a structure that determines whether or not to make the general cells or the redundant cells, which are used to repair the defective cells, active when the semiconductor memory apparatus operates in a normal state, that is, a repair set is necessarily prepared.
As shown in FIG. 1, a semiconductor memory apparatus according to the related art includes cell blocks 10, redundant cells 11, a refresh address counter 20, a pre-decoder 30, repair sets 40, and decoders 50.
The refresh address counter 20 counts a refresh address RA when a refresh signal REF is enabled.
The pre-decoder 30 pre-decodes the refresh address RA and a normal address NA that corresponds to a read or write command.
The refresh address RA is counted such that general cells in each of the cell blocks 10 can be sequentially activated.
The number of the repair sets 40 may vary according to a circuit design or the number of the redundant cells 11. In FIG. 1, some of the cell blocks 10 are shown among all of the cell blocks, and the redundant cells 11 are formed above and below each of the cell blocks 10. Therefore, two of the repair sets 40 are also formed at each of the cell blocks 10, for example.
As shown in FIG. 2, each of the repair sets 40 includes a first transistor M1 that has a source connected to a power supply terminal and a gate receiving a precharge signal PCG, a plurality of second transistors M2 that have gates individually receiving addresses A0 to An, which are output by the pre-decoder 30, a plurality of fuses F, each of which has one end connected to a drain of the first transistor M1 and the other end connected to a source of each of the plurality of second transistors M2, first and second inverters IV1 and IV2 that are connected to one end of the final fuse F among the plurality of fuses F, and a third transistor M3 that has a gate receiving output of the first inverter IV1, a source connected to the power supply terminal, and a drain connected to an input terminal of the first inverter IV1. When a defective cell is found among the cells of the cell blocks 10 and repaired using the redundant cell 11, the fuse F, which is connected to the second transistor M2, among the plurality of fuses F is removed. Here, the second transistor M2 receives an address (i.e., any one of the addresses A0 to An) of the repaired cell.
The repair set 40 precharges a node 1 with a high level according to the precharge signal PCG. A redundant enable signal REDEN remains enabled at a high level according to a latch operation of the first inverter IV1 and the third transistor M3. When the addresses A0 to An that are output by the pre-decoder 30 are not repaired, the corresponding fuses F are not cut off. Therefore, the node 1 is connected to a ground and thus the redundant enable signal REDEN is disabled at a low level.
Meanwhile, when the addresses A0 to An output by the pre-decoder 30 are repaired addresses, the corresponding fuses F are cut off. Therefore, the node 1 does not become a low level, and the redundant enable signal REDEN is maintained at a high level, that is, in an enabled state.
The redundant enable signal REDEN is output to the redundant cell 11. When the redundant enable signal REDEN is enabled, the corresponding redundant cell 11 becomes active.
The decoder 50 decodes the outputs of the pre-decoder 30 so as to generate row addresses, and outputs the row addresses to the cell block 11.
When the redundant enable signal REDEN is enabled, the decoder 50 does not allow the row addresses, which are obtained by decoding the outputs of the pre-decoder 30, to be output to the cell block 11.
The decoder 50 receives the same addresses as those of the repair set 40 and performs its operation. When the redundant enable signal REDEN is enabled, since the cells corresponding to the row addresses that the decoder 50 outputs are repaired using the redundant cells 11, the decoder 50 disables the row addresses.
As described above, the repair sets 40 always operate during a refresh operation as well as a normal operation.
The semiconductor memory apparatus according to the related art increases a refresh current because the repair sets always operate during the refresh operation. Further, the refresh current is one of the important factors that determine performance of the semiconductor memory apparatus. Therefore, the performance of the semiconductor memory apparatus may be lowered due to an increase in the refresh current.